List of Archived Posts
2002 Newsgroup Postings (08/29 - 09/12)
- What is microcode?
- Superhot coffee
- What is microcode?
- why is Kerberos better than this simpler replacement
- why is Kerberos better than this simpler replacement
- What good is RSA when using passwords ?
- Computer Architectures
- What is microcode?
- PDP-11 Clones was Re: Why did AMD opt for so few registers in
- Moore law
- What is microcode?
- IEEE article on intelligence and security
- IEEE article on intelligence and security
- notwork
- Z/OS--anything new?
- Large Banking is the only chance for Mainframe
- Large Banking is the only chance for Mainframe
- What is microcode?
- ISAs, SMP and hardware optimisations
- Computer Architectures
- Backdoor in AES ?
- Free CPU (was: PDP-11 Clones)
- Computer Architectures
- Moore law
- Two questions on HMACs and hashing
- Do any architectures use instruction count instead of timer
- Do any architectures use instruction count instead of timer
- End of Moore's law and how it can influence job market
- Two questions on HMACs and hashing
- Do any architectures use instruction count instead of timer
- Do any architectures use instruction count instead of timer
- Do any architectures use instruction count instead of timer
- What is microcode?
- misc resource manager related folklore postings
- Do any architectures use instruction count instead of timer
- Cryptography
- Do any architectures use instruction count instead of timer
- Computer Architectures
- Backdoor in AES ?
- Moore law
- Do any architectures use instruction count instead of timer
- 10 choices that were critical to the Net's success
- Thirty Years Later: Lessons from the Multics Security Evaluation
- another 30 year thing
- Thirty Years Later: Lessons from the Multics Security Evaluation
- Thirty Years Later: Lessons from the Multics Security Evaluation
- 10 choices that were critical to the Net's success
- Do any architectures use instruction count instead of timer
- 10 choices that were critical to the Net's success
- Do any architectures use instruction count instead of timer
- IBM 2311 disk drive actuator and head assembly
- Handling variable page sizes?
- Itanium2 performance data from SGI
- 10 choices that were critical to the Net's success
- 10 choices that were critical to the Net's success
- The problem with installable operating systems
- 10 choices that were critical to the Net's success
- Handling variable page sizes?
- Spin Loop?
- Spin Loop?
- Handling variable page sizes?
- 10 choices that were critical to the Net's success
- Itanium2 performance data from SGI
- 10 choices that were critical to the Net's success
- 10 choices that were critical to the Net's success
- The problem with installable operating systems
- 10 choices that were critical to the Net's success
- The problem with installable operating systems
- 10 choices that were critical to the Net's success
- The problem with installable operating systems
- Al Gore and Fidonet [was: 10 choices]
- Faster seeks (was Re: Do any architectures use instruction
What is microcode?
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: What is microcode?
Newsgroups: comp.arch
Date: Thu, 29 Aug 2002 23:16:01 GMT
grandflashfunk@yahoo.com (Brian Nichols) writes:
Can anyone explain what microcode is? How is it different from assembly?
some discussions
http://www.garlic.com/~lynn/subtopic.html#360mcode 360/370 m'code
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Superhot coffee
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Superhot coffee
Newsgroups: rec.arts.sf.science,rec.arts.sf.written,alt.folklore.computers
Date: Fri, 30 Aug 2002 13:26:38 GMT
hawk@slytherin.ds.psu.edu (Dr. Richard E. Hawkins) writes:
Thanks. I needed this badly. I've been searching for a sensible
California law for my business law class, to offset all the really
screwy stuff I have to explain . . .
when i first moved to mass., somebody pointed out to me that the same
week cal. legislature passed a bill requiring min. 2yr degree for
highway patrol, mass leg. defeated a bill requiring min. high school
for highway patrol.
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
What is microcode?
Refed: **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: What is microcode?
Newsgroups: comp.arch,alt.folklore.computers
Date: Fri, 30 Aug 2002 17:20:35 GMT
"Rupert Pigott" writes:
I always thought of Microcode as being a sort of "input stream
decompressor" rather than an interpreter. Mind you with VAX-11
instructions you could be forgiven for treating it as an
interpreter... Jeez... :)
360 & 370 were microcoded machines (few exceptions) ... i.e. there was
a native processor engine and then the programming that implemented
360/370 architecture. the lower-end machines tended to be (sequential)
vertical m'code (i.e. looks a lot machine/assembler) and use to run
something like 10:1 (i.e. .5mip 370 engine had a 5mip microprocessor
engine). Somewhat blurred distinction between 360 m'code ... and the
current generation of 390 emulators running on intel architecture.
the higher end 360/370 tended to be horizontal m'code ... one m'code
instruction per cycle and lots of bits controlling numerous
(overlapped) functions (m'code programmer that started some operation
... like fetch ... needed to count instructions/cycles before fetch
was finished and data was available). Efficiency of m'code tended to
be measured in avg. cycles per instruction (since there was some
amount of concurrent processing). For instance, various m'code
enhancements helped reduce the avg cycle/instruction of 2.1 in the
370/165 to 1.6 in the 370/168.
random
http://www.garlic.com/~lynn/subtopic.html#360mcode
all the various ancillary processors in a mainframe (channels,
controller, devices) were frequently various kinds of m'code
programmed engines of various kinds. They could be somewhat considered
embedded controllers in today's terms with really blurry distinction
between calling these microcode or machine code. Some of the early
801/RISC chip efforts were targeted at the area. The 3830 disk
controller was a horizontal m'code engine. The follow-on for the 3880
disk controller was jib-prime (veritical m'code) chip.
random
http://www.garlic.com/~lynn/subtopic.html#disk
when I was an undergraduate I worked on the first 360 plug-compatible
controller. It started with a Interdata/3 minicomputer. A 360 channel
interface board was built for the Interdata and it was programmed to
emulate the 2702 terminal controller.
random
http://www.garlic.com/~lynn/subtopic.html#360pcm
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
why is Kerberos better than this simpler replacement
Refed: **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: why is Kerberos better than this simpler replacement
Newsgroups: sci.crypt
Date: Sat, 31 Aug 2002 14:09:35 GMT
Paul Rubin <phr-n2002b@NOSPAMnightsong.com> writes:
At the time Kerberos was developed, anything using public key was tied
up by patents, so they chose to stay with symmetric keys.
pk-init has been hacking(?) around in the ietf kerberos group for some
time (initial kerberos authentication with public key). draft 15 had
its 6month expire the end of may and i've yet to see draft 16
.. although place-holder is there:
http://web.archive.org/web/20021112170430/http://www.ietf.cnri.reston.va.us/internet-drafts/draft-ietf-cat-kerberos-pk-init-16.txt
some general ietf kerberos
http://web.archive.org/web/20030520011552/http://www.ietf.cnri.reston.va.us/ids.by.wg/krb-wg.html
general kerberos
http://web.mit.edu/kerberos/www/index.html
misc. refs:
http://www.garlic.com/~lynn/aadsm11.htm#40 ALARMED ... Only Mostly Dead ... RIP PKI ... part II
http://www.garlic.com/~lynn/aepay10.htm#33 pk-init draft (not yet a RFC)
http://www.garlic.com/~lynn/aepay10.htm#39 Microsoft Trustbridge ... Kerberos (tickets) support
http://www.garlic.com/~lynn/2002j.html#60 How to map a user account to a digital cert?
in some sense, pk-init (for kerberos) is very similar to the aads
proposal i made for radius some time ago.
http://www.garlic.com/~lynn/subtopic.html#radius
general aads
http://www.garlic.com/~lynn/x959.html#aads
from one point of view, the issue for a "from scratch" protocol
... isn't the actual bits traveling over the wire; by far the greatest
effort is all the administrative infrastructure needed to maintain and
support the infrastructure (which easily can be a couple orders of
magnitude larger effort than the bits on the wire effort). if you
don't like kerberos ... crafting some different "bits on the wire"
(like aads public key) on the side of a radius implementation would
leverage an existing administrative infrastructure. one of the
advantages of kerberos (as well as radius) is large body of
infrastructures that already have the support (again the "bits on the
wire" can be totally dwarfed by the administrative infrastructure
needed to support correct and timely information).
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
why is Kerberos better than this simpler replacement
Refed: **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: why is Kerberos better than this simpler replacement
Newsgroups: sci.crypt
Date: Sat, 31 Aug 2002 17:32:06 GMT
Daniel James writes:
Kerberos is an attempt to solve a particular distributed
access control problem without using PKI. If you remove
that constraint any number of better solutions become
possible.
pk-init allows for either PKI (aka CADS) or AADS type operation
... aka previous post
http://www.garlic.com/~lynn/2002l.html#3 why is kerberos better than this simpler replacement
radius is possible with password, challenge/response, and is possible to
enhance for aads type operation ... with aads chip strawman
http://www.garlic.com/~lynn/x959.html#aads
http://www.garlic.com/~lynn/subpubkey.html#radius
for general radius rfc ...
http://www.garlic.com/~lynn/rfcietff.htm
and click on Term (term->RFC#) and then click on "RADIUS" in Acronym
fastpath, aka:
remote authentication dial in user service (RADIUS )
see also authentication , network access server , network services
3162 2882 2869 2868 2867 2866 2865 2809 2621 2620 2619 2618 2548 2139
2138 2059 2058
general kerberos RFCs (you have to scroll for, note pk-init is still
draft as per prior post, not RFC):
kerberos
see also authentication , security
3244 3129 2942 2712 2623 1964 1510 1411
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
What good is RSA when using passwords ?
Refed: **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: What good is RSA when using passwords ?
Newsgroups: sci.crypt
Date: Sat, 31 Aug 2002 20:46:14 GMT
"Skybuck Flying" writes:
Using RSA solves nothing in this case, so I could just leave RSA out safe
myself some possible RSA bugs and use symetric encryption like AES all the
way :)
asymmetric reduces the effort in distributing verification data (aka
the public key). in simple shared-secret exchange ... MITM is somewhat
mitigated since they may only have to concentrate or pair-wise
communication .... which nominal force some sort of out-of-band process.
note, however that some of the asymmetric solutions for out-of-band
process aren't easily/possible in the shared-secret paradigm ... since
the shared-secret can not only be used to verify data (decrypt) but
also originate data (encrypt) .... where-as a public key is only used
for verification (private key for originating isn't divulge). A public
key can get published publicly in multiple places, increasing the
number of different points of compromise for MITM (aka web-of-trust).
Furthermore, what is being published is not a shared-secret (allowing
both verification as well of origination to occur). In fact, the
increase in complexity associated with PKI/CADS paradigm can bring
with it a whole new set of (possibly quite obscure) vulnerabilities.
Note that PKI/CADS paradigm for asymmetric can still have a single
point of compromise ... aka the specific certification authority
and/or several (possibly quite complicated) business processes used by
a certification authority; aka a PKI/CADS paradigm can have a large
number of single point of failure .... any one being compromised can
compromise the whole infrastructure (this is sometimes referred to as
systemic risk).
Now there are a couple different scenarios where passwords may be
used. One involves protecting access & use of the private key
.... this is nominal referred to as a secret (only you know the secret
... ideally nobody else has access to it).
Note however, passwords are also used in shared-secret scenario (same
character string, different semantics). Nominally asymmetric is
targeted at replacing shared-secret operations .... eliminating the
sharing of something that can both originate as well as verify
transaction.
random past shared-secret and MITM threads:
http://www.garlic.com/~lynn/aepay10.htm#37 landscape & p-cards
http://www.garlic.com/~lynn/aadsm10.htm#biometrics biometrics
http://www.garlic.com/~lynn/aadsm10.htm#bio3 biometrics (addenda)
http://www.garlic.com/~lynn/aadsm10.htm#bio5 biometrics
http://www.garlic.com/~lynn/aadsm10.htm#bio6 biometrics
http://www.garlic.com/~lynn/aadsm10.htm#bio7 biometrics
http://www.garlic.com/~lynn/aadsm10.htm#bio8 biometrics (addenda)
http://www.garlic.com/~lynn/aadsm11.htm#17 Alternative to Microsoft Passport: Sunshine vs Hai
http://www.garlic.com/~lynn/aadsm11.htm#20 IBM alternative to PKI?
http://www.garlic.com/~lynn/aadsm11.htm#39 ALARMED ... Only Mostly Dead ... RIP PKI .. addenda
http://www.garlic.com/~lynn/aadsm12.htm#4 NEWS: 3D-Secure and Passport
http://www.garlic.com/~lynn/aadsm12.htm#5 NEWS: 3D-Secure and Passport
http://www.garlic.com/~lynn/aadsm12.htm#8 [3d-secure] 3D Secure and EMV
http://www.garlic.com/~lynn/2000.html#39 "Trusted" CA - Oxymoron?
http://www.garlic.com/~lynn/2000b.html#53 Digital Certificates-Healthcare Setting
http://www.garlic.com/~lynn/2000b.html#90 Question regarding authentication implementation
http://www.garlic.com/~lynn/2000b.html#92 Question regarding authentication implementation
http://www.garlic.com/~lynn/2000f.html#4 Why trust root CAs ?
http://www.garlic.com/~lynn/2000f.html#78 TSS ancient history, was X86 ultimate CISC? designs)
http://www.garlic.com/~lynn/2000g.html#5 e-commerce: Storing Credit Card numbers safely
http://www.garlic.com/~lynn/2000g.html#33 does CA need the proof of acceptance of key binding ?
http://www.garlic.com/~lynn/2000g.html#34 does CA need the proof of acceptance of key binding ?
http://www.garlic.com/~lynn/2000g.html#49 Use of SET?
http://www.garlic.com/~lynn/2001.html#68 California DMV
http://www.garlic.com/~lynn/2001b.html#0 Java as a first programming language for cs students
http://www.garlic.com/~lynn/2001c.html#30 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#34 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#39 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#40 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#41 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#42 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#44 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#45 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#50 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#54 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#60 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#63 SSL weaknesses
http://www.garlic.com/~lynn/2001d.html#36 solicit advice on purchase of digital certificate
http://www.garlic.com/~lynn/2001e.html#83 The Mind of War: John Boyd and American Security
http://www.garlic.com/~lynn/2001f.html#25 Question about credit card number
http://www.garlic.com/~lynn/2001f.html#31 Remove the name from credit cards!
http://www.garlic.com/~lynn/2001h.html#5 PKI/Digital signature doesn't work
http://www.garlic.com/~lynn/2001h.html#7 PKI/Digital signature doesn't work
http://www.garlic.com/~lynn/2001h.html#10 VM: checking some myths.
http://www.garlic.com/~lynn/2001h.html#58 Net banking, is it safe???
http://www.garlic.com/~lynn/2001i.html#9 Net banking, is it safe???
http://www.garlic.com/~lynn/2001i.html#16 Net banking, is it safe???
http://www.garlic.com/~lynn/2001i.html#25 Net banking, is it safe???
http://www.garlic.com/~lynn/2001i.html#28 Proper ISA lifespan?
http://www.garlic.com/~lynn/2001i.html#35 Net banking, is it safe???
http://www.garlic.com/~lynn/2001i.html#36 Net banking, is it safe???
http://www.garlic.com/~lynn/2001i.html#57 E-commerce security????
http://www.garlic.com/~lynn/2001j.html#0 E-commerce security????
http://www.garlic.com/~lynn/2001j.html#2 E-commerce security????
http://www.garlic.com/~lynn/2001j.html#9 E-commerce security????
http://www.garlic.com/~lynn/2001j.html#49 Are client certificates really secure?
http://www.garlic.com/~lynn/2001j.html#52 Are client certificates really secure?
http://www.garlic.com/~lynn/2001k.html#1 Are client certificates really secure?
http://www.garlic.com/~lynn/2001k.html#34 A thought on passwords
http://www.garlic.com/~lynn/2001k.html#58 I-net banking security
http://www.garlic.com/~lynn/2001k.html#61 I-net banking security
http://www.garlic.com/~lynn/2001m.html#5 Smart Card vs. Magnetic Strip Market
http://www.garlic.com/~lynn/2001m.html#41 Solutions to Man in the Middle attacks?
http://www.garlic.com/~lynn/2001n.html#94 Secret Key Infrastructure plug compatible with PKI
http://www.garlic.com/~lynn/2002.html#9 How to get 128-256 bit security only from a passphrase?
http://www.garlic.com/~lynn/2002c.html#4 Did Intel Bite Off More Than It Can Chew?
http://www.garlic.com/~lynn/2002c.html#5 Did Intel Bite Off More Than It Can Chew?
http://www.garlic.com/~lynn/2002c.html#7 Opinion on smartcard security requested
http://www.garlic.com/~lynn/2002c.html#10 Opinion on smartcard security requested
http://www.garlic.com/~lynn/2002c.html#31 You think? TOM
http://www.garlic.com/~lynn/2002d.html#4 IBM Mainframe at home
http://www.garlic.com/~lynn/2002d.html#43 Mainframers: Take back the light (spotlight, that is)
http://www.garlic.com/~lynn/2002d.html#47 SSL MITM Attacks
http://www.garlic.com/~lynn/2002d.html#50 SSL MITM Attacks
http://www.garlic.com/~lynn/2002e.html#17 Smart Cards
http://www.garlic.com/~lynn/2002e.html#18 Opinion on smartcard security requested
http://www.garlic.com/~lynn/2002e.html#23 Opinion on smartcard security requested
http://www.garlic.com/~lynn/2002e.html#36 Crypting with Fingerprints ?
http://www.garlic.com/~lynn/2002e.html#40 Smart Cards
http://www.garlic.com/~lynn/2002e.html#60 Browser Security
http://www.garlic.com/~lynn/2002f.html#45 Biometric Encryption: the solution for network intruders?
http://www.garlic.com/~lynn/2002g.html#65 Real man-in-the-middle attacks?
http://www.garlic.com/~lynn/2002h.html#11 Why did OSI fail compared with TCP-IP?
http://www.garlic.com/~lynn/2002h.html#12 Why did OSI fail compared with TCP-IP?
http://www.garlic.com/~lynn/2002h.html#40 [survey] Possestional Security
http://www.garlic.com/~lynn/2002j.html#14 Symmetric-Key Credit Card Protocol on Web Site
http://www.garlic.com/~lynn/2002j.html#18 Symmetric-Key Credit Card Protocol on Web Site
http://www.garlic.com/~lynn/2002j.html#38 MITM solved by AES/CFB - am I missing something?!
http://www.garlic.com/~lynn/2002j.html#58 SSL integrity guarantees in abscense of client certificates
http://www.garlic.com/~lynn/2002j.html#63 SSL integrity guarantees in abscense of client certificates
http://www.garlic.com/~lynn/2002k.html#11 Serious vulnerablity in several common SSL implementations?
http://www.garlic.com/~lynn/2002k.html#51 SSL Beginner's Question
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Computer Architectures
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Computer Architectures
Newsgroups: comp.arch
Date: Sat, 31 Aug 2002 21:04:28 GMT
nmm1@cus.cam.ac.uk (Nick Maclaren) writes:
The vibes from Cray are mixed. I really don't know what they are
up to at all.
which cray? ... cray research? ... made those supercomputers ... got
bought by SGI ... some revamping ... and then sold off to Tera?
http://web.archive.org/web/20021201102300/http://tera.com/
http://web.archive.org/web/20021224224948/http://cray.com/news/0003/acquisition.html
http://web.archive.org/web/20021224221146/http://cray.com/news/0004/acq-close.html
Seattle, Washington -- April 4, 2000 -- Tera Computer Company (Nasdaq
NM: TERA), a leading designer of high-performance computer systems,
announced today that it has closed its acquisition of the Cray vector
supercomputer business unit, and the Cray brand name from SGI (NYSE:
SGI). The definitive agreement to acquire Cray was previously
announced on March 2, 2000. The acquisition was made in exchange for
$15 million in cash, one million shares of unregistered common stock
and a nine-month promissory note in the amount of $36.3 million
subject to adjustment upon final audit.
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
What is microcode?
Refed: **, - **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: What is microcode?
Newsgroups: comp.arch,alt.folklore.computers
Date: Sun, 01 Sep 2002 14:44:03 GMT
jmfbahciv writes:
No wonder I'm terribly confused. To me, ROM implies read-only memory
but I hear of BIOSes getting updated which implies a writable thingie.
BIOS ... ROM, FLASH, PROM, EEPROM, etc. ROM might be real read-only
memory, PROM is programmable read-only memory i.e. you can change it
... but it may be a little harder to change than standard r/w memory.
BIOS tends to be more like system calls in ROM/PROM than 360/370
microcode. as been mentioned by others ... 360 m'code could be in
something that looked like punch cards made of mylar (could be
programmed manually). Customers rarely got involved in writing m'code,
the wrote stuff for the 360.
number of the 370 (processor, controllers, devices) started out with
the original floppy disks for "microcode" which would automatically
load at power-on. processors like 370/145 had standard room for m'code
but it could overflow into the "top" of processor memory. any m'code
overflow would reset the standard processor addressable memory to
account for that taken up by m'code.
3081 got even more complex ... it had a uc.5 microprocessor (used in
37xx controllers and the 8100 computer) as a "service processor" and a
piccolo (60?mbyte) hard drive. The uc.5 would boot at power-on and
read everything for the 3081 m'code from the piccolo. Functions like
boot/IPL were transactions with the code running on the uc.5 service
processor. M'code went into fixed amount of storage ... in some cases
references were made to m'code that wasn't currently loaded (typically
very low useage) and the uc.5 would "page" it. As you can imagine,
having to page m'code could slow things down a bit.
The 3090 had a pair of "370s" as service processors (actually pair of
4361s) running a customized version of vm/370 release 6. The 4361s
would boot VM/370 and bring up the various service processor functions
and load whatever stuff was needed into the 3090. Booting the 3090
then was function of interacting with the service processor function.
random refs:
http://www.garlic.com/~lynn/subtopic.html#360mcode
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
PDP-11 Clones was Re: Why did AMD opt for so few registers in
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: PDP-11 Clones was Re: Why did AMD opt for so few registers in
x86-64?
Newsgroups: comp.arch,alt.folklore.computers
Date: Sun, 01 Sep 2002 18:32:11 GMT
Eric Smith <eric-no-spam-for-me@brouhaha.com> writes:
I figured out for myself how to do this in a bitmapped display in 1977,
when I was a 13 years old novice programmer. I distributed several
programs that used the technique. None were published commercially,
so I suppose the patent office wouldn't have accepted them as prior
art.
it just has to be public ... not commercially and it can even be by
you (in the case you made something public before patent
application). I got caught on something by including it in a seminar
at ISI/USC (not commercial). also I got the impression that if you
know of pertinent material (things like prior/related art) you are
suppose to include it in your patent application (or it could possibly
be grounds for invalidating the patent application).
The rules are different in the US and PCT. US, you have up to a year
after you have publicly divulged something to file. PCT, you can't
file something after it has been divulged publicly.
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Moore law
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Moore law
Newsgroups: comp.arch
Date: Sun, 01 Sep 2002 20:57:11 GMT
Tim Bradshaw writes:
This I mostly disagree with. I agree about hardware (thus, perhaps
removing this thread's last bit of relevance to comp.arch), but I
think that although it is clearly possible to write C code which is
safe, it is a sufficient burden on the average programmer (and average
code is written by average programmers) that they will not do that.
I'm an average programmer, I suppose, and I am not at all convinced
by my ability to write safe code in C. In general, high-level
languages are there to make our lives easier while making the
machine's life more difficult, and I think that this is one place
they could make a significant difference.
my assertion is that the semantics of common C string libraries
contribute significantly to C code vulnerabilities, vulnerabilities
that are significantly lower occurance (one to two order magnitude) in
environments with better semantics ... which is counter argument to it
being (just) a hardware/software issue.
something that is fairly common across a lot of environments is
dangling pointers associated with dynamic storage
allocation/deallocation and in some cases, some relavance to system
serialization primitives.
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
What is microcode?
Refed: **, - **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: What is microcode?
Newsgroups: comp.arch,alt.folklore.computers
Date: Mon, 02 Sep 2002 14:52:26 GMT
jmfbahciv writes:
Whenever I hear about stuff like this, the picture that
immediately pops up is of the guy who has set up 10,000
dominoes and a bug drops in.
in fact that is sort of the reason it was done. Field Engineering had
a requirement that they could do "bootstrap" diagnostic in the field,
starting with a scope on the simplest part and going to more and more
complex components. TCMs used in later processors were no longer
scope'able. So the cascade goes that the service processor was
scopable and could be field diagnosed (and if necessary replaced). The
service processor had all sorts of probes into all parts of the system
(including the TCMs) ... and the service processor could be used to
"scope"/diagnose the rest of the system. The 3090 had redundant
"service processors" (4361s) ... so that even if one failed ... the
other was available.
random tcm refs:
http://www.garlic.com/~lynn/2000b.html#36 How to learn assembler language for OS/390 ?
http://www.garlic.com/~lynn/2000b.html#37 How to learn assembler language for OS/390 ?
http://www.garlic.com/~lynn/2000b.html#38 How to learn assembler language for OS/390 ?
http://www.garlic.com/~lynn/2000d.html#61 "all-out" vs less aggressive designs (was: Re: 36 to 32 bit transition)
http://www.garlic.com/~lynn/2001j.html#13 Parity - why even or odd (was Re: Load Locked (was: IA64 running out of steam))
http://www.garlic.com/~lynn/2001k.html#7 hot chips and nuclear reactors
http://www.garlic.com/~lynn/2002b.html#3 Microcode? (& index searching)
http://www.garlic.com/~lynn/2002d.html#13 IBM Mainframe at home
http://www.garlic.com/~lynn/2002e.html#20 What goes into a 3090?
& service processor:
http://www.garlic.com/~lynn/96.html#41 IBM 4361 CPU technology
http://www.garlic.com/~lynn/99.html#61 Living legends
http://www.garlic.com/~lynn/99.html#62 Living legends
http://www.garlic.com/~lynn/99.html#108 IBM 9020 computers used by FAA (was Re: EPO stories (was: HELP IT'S HOT!!!!!))
http://www.garlic.com/~lynn/2000b.html#50 VM (not VMS or Virtual Machine, the IBM sort)
http://www.garlic.com/~lynn/2000b.html#51 VM (not VMS or Virtual Machine, the IBM sort)
http://www.garlic.com/~lynn/2000c.html#76 Is a VAX a mainframe?
http://www.garlic.com/~lynn/2000d.html#26 Superduper computers--why RISC not 390?
http://www.garlic.com/~lynn/2001b.html#83 Z/90, S/390, 370/ESA (slightly off topic)
http://www.garlic.com/~lynn/2001h.html#2 Alpha: an invitation to communicate
http://www.garlic.com/~lynn/2002.html#45 VM and/or Linux under OS/390?????
http://www.garlic.com/~lynn/2002b.html#32 First DESKTOP Unix Box?
http://www.garlic.com/~lynn/2002b.html#44 PDP-10 Archive migration plan
http://www.garlic.com/~lynn/2002c.html#42 Beginning of the end for SNA?
http://www.garlic.com/~lynn/2002e.html#5 What goes into a 3090?
http://www.garlic.com/~lynn/2002e.html#19 What goes into a 3090?
http://www.garlic.com/~lynn/2002i.html#79 Fw: HONE was .. Hercules and System/390 - do we need it?
http://www.garlic.com/~lynn/2002j.html#28 ibm history note from vmshare
http://www.garlic.com/~lynn/2002l.html#7 What is microcode?
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
IEEE article on intelligence and security
Refed: **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: IEEE article on intelligence and security
Newsgroups: sci.crypt
Date: Mon, 02 Sep 2002 15:08:56 GMT
"Harris Georgiou" writes:
This is a very critical point most people miss. The goal always is to gain
access to the information using every possible way, not just crack the
opponent's encryption. Instead of breaking into any PGP-like application,
it's much easier to exploit the user's poor security habits (people STILL
use their names and birthdays as passwords).
somewhat related ... security proportional to risk:
http://www.garlic.com/~lynn/2001h.html#61 Security Proportional To Risk
and
http://www.garlic.com/~lynn/2001j.html#5 E-commerce security????
all of the major exploits that have been in the press have had nothing
to do with the cryptography.
http://www.garlic.com/~lynn/subtopic.html#fraud
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
IEEE article on intelligence and security
Refed: **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: IEEE article on intelligence and security
Newsgroups: sci.crypt
Date: Mon, 02 Sep 2002 16:28:30 GMT
Anne & Lynn Wheeler writes:
somewhat related ... security proportional to risk:
or lets erect a 4' thick bank vault door in an open space ... and
convince everybody that they should ignore the fact that the space has
no walls and that they should only attempt to penetrate the area by
compromising the vault door.
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
notwork
Refed: **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: notwork
Newsgroups: alt.folklore.computers
Date: Mon, 02 Sep 2002 20:00:45 GMT
re:
http://www.garlic.com/~lynn/2002k.html#61 arrogance metrics (Benoits)
so my wife had this meeting with the corporate CFO to discuss continued
funding of hsdt
http://www.garlic.com/~lynn/subtopic.html#hsdt
he had just come from an executive board meeting where there had been
presentation by somebody from communication group about the internal
network was going to shortly collapse unless they quickly converted to
SNA ... and he wanted to know what she thot about the claim ...
BLAAA!!! CENSORED ... sorry
raondom other stuff:
http://www.garlic.com/~lynn/93.html#28 Log Structured filesystems -- think twice
http://www.garlic.com/~lynn/94.html#33b High Speed Data Transport (HSDT)
http://www.garlic.com/~lynn/96.html#14 mainframe tcp/ip
http://www.garlic.com/~lynn/96.html#15 tcp/ip
http://www.garlic.com/~lynn/96.html#17 middle layer
http://www.garlic.com/~lynn/98.html#34 ... cics ... from posting from another list
http://www.garlic.com/~lynn/98.html#49 Edsger Dijkstra: the blackest week of his professional life
http://www.garlic.com/~lynn/98.html#50 Edsger Dijkstra: the blackest week of his professional life
http://www.garlic.com/~lynn/99.html#36 why is there an "@" key?
http://www.garlic.com/~lynn/99.html#123 Speaking of USB ( was Re: ASR 33 Typing Element)
http://www.garlic.com/~lynn/2000.html#90 Ux's good points.
http://www.garlic.com/~lynn/2000b.html#69 oddly portable machines
http://www.garlic.com/~lynn/2000b.html#78 "Database" term ok for plain files?
http://www.garlic.com/~lynn/2000c.html#59 Does the word "mainframe" still have a meaning?
http://www.garlic.com/~lynn/2000e.html#45 IBM's Workplace OS (Was: .. Pink)
http://www.garlic.com/~lynn/2000f.html#30 OT?
http://www.garlic.com/~lynn/2001d.html#63 Pentium 4 Prefetch engine?
http://www.garlic.com/~lynn/2001d.html#65 Pentium 4 Prefetch engine?
http://www.garlic.com/~lynn/2001e.html#52 Pre ARPAnet email?
http://www.garlic.com/~lynn/2001g.html#33 Did AT&T offer Unix to Digital Equipment in the 70s?
http://www.garlic.com/~lynn/2001h.html#44 Wired News :The Grid: The Next-Gen Internet?
http://www.garlic.com/~lynn/2001j.html#20 OT - Internet Explorer V6.0
http://www.garlic.com/~lynn/2001m.html#25 ESCON Data Transfer Rate
http://www.garlic.com/~lynn/2002.html#11 The demise of compaq
http://www.garlic.com/~lynn/2002.html#28 Buffer overflow
http://www.garlic.com/~lynn/2002i.html#43 CDC6600 - just how powerful a machine was it?
http://www.garlic.com/~lynn/2002i.html#45 CDC6600 - just how powerful a machine was it?
http://www.garlic.com/~lynn/2002j.html#67 Total Computing Power
http://www.garlic.com/~lynn/2002k.html#12 old/long NSFNET ref
http://www.garlic.com/~lynn/2002k.html#20 Vnet : Unbelievable
http://www.garlic.com/~lynn/2002k.html#31 general networking is: DEC eNet: was Vnet : Unbelievable
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Z/OS--anything new?
Refed: **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Z/OS--anything new?
Newsgroups: alt.folklore.computers
Date: Tue, 03 Sep 2002 18:28:34 GMT
lwinson@bbs.cpcn.com (lwin) writes:
For a lot of us, the "IBM mainframe operating system" means to code
DISP=(NEW,CATLG,DELETE), and looking at the condition code at the end
of a job's run. We don't get that involved with the stuff behind the
scenes.
In the old days, when CPU time, core memory, and DASD memory were
scarce we were a lot more conscious of the hardware environment since
we had to allow for big critical jobs taking up the whole machine, and
requesting and allocating resources that we needed for a particular
job. Some years ago, "silos" with tape carts replaced reels of tape
and requesting a pull from the tape library. Massive volumes of cheap
DASD eliminated the need to put a lot of stuff on tape/cart
altogether.
So today, a lot of things we had to do in the past have been
eliminated. Along with that, gone is knowing what kind of CPU and
peripherals are running since there is no need to. Further, in large
organizations, those things are often changing--multiple CPUs being
brought together or split up again, upgrades in DASD and CPUs, etc.
Unless one makes an conscious effort to keep up, most people wouldn't
know of these changes. Further, changes such as this usually affect
the systems programmers the most, with relatively little affecting
application programmers.
i've asserted that before PCs there was possibly as much or more
online systems that were ibm mainframe based as any other online
system out there ... but because people were so pre-occupied with the
DISP= varietry ... that online/time-sharing system from other vendors
got a lot more notice aka lots of people may identity some other
vendor with the concept of online & time-sharing .... even tho
there may have been significant more of the ibm variety; it was just
that the DISP= variety of ibm mainframe so dwarfed the
online/time-sharing variety (except possibly for internal ibm network,
development, business).
in the early '80s there was a lot of attention that there were a
variety/number of different ibm mainframe kernels each with unique
low-level hardware & device support ... and there was essentially
totally replicated costs for each one. There was a project to look at
doing a common kernel that would eliminate the replicated costs. For
some purely accidental reasons ... the project got referred to as "ZM"
(this is almost 20 years ago).
some of the stuff leading up to "ZM" was programming technology,
hardware assurance, etc.
http://www.garlic.com/~lynn/96.html#4a John Hartmann's Birthday Party
http://www.garlic.com/~lynn/2001l.html#25 mainframe question
http://www.garlic.com/~lynn/2001m.html#53 TSS/360
http://www.garlic.com/~lynn/2001n.html#46 Blinking lights
note that part of started in the fort knox period where 801
processors were going to become the common microcode engine across the
corporation
http://www.garlic.com/~lynn/2000d.html#60 "all-out" vs less aggressive designs (was: Re: 36 to 32 bit transition)
http://www.garlic.com/~lynn/2001f.html#43 Golden Era of Compilers
http://www.garlic.com/~lynn/2001h.html#69 Very CISC Instuctions (Was: why the machine word size ...)
http://www.garlic.com/~lynn/2002g.html#39 "Soul of a New Machine" Computer?
http://www.garlic.com/~lynn/2002g.html#70 Pipelining in the past
http://www.garlic.com/~lynn/2002h.html#19 PowerPC Mainframe?
http://www.garlic.com/~lynn/2002h.html#63 Sizing the application
http://www.garlic.com/~lynn/2002i.html#81 McKinley Cometh
http://www.garlic.com/~lynn/2002j.html#20 MVS on Power (was Re: McKinley Cometh...)
http://www.garlic.com/~lynn/99.html#136a checks (was S/390 on PowerPC?)
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Large Banking is the only chance for Mainframe
Refed: **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Large Banking is the only chance for Mainframe
Newsgroups: bit.listserv.ibm-main
Date: Tue, 03 Sep 2002 16:07:20 GMT
"Howard Brazee" writes:
Why should mainframes be limited to batch processing? Why do banks
use more batch processing than everybody else?
We are getting bigger and bigger databases - shouldn't these databases
be most efficiently run on systems that fit them? We are recognizing
new security and privacy needs. Our needs for large amounts of
processing are different than they used to be - but they aren't
smaller, they are bigger.
Sure, if the "database" consists of web pages that don't absolutely
have to be coördinated. But lots of our needs have real-time
processing that have to handle lots of data in a big hurry - with
security and privacy checks. That implies a need for centralized
power. What are the alternatives that can grow into appropriate
solutions?
there are some trade-offs between mission/business critical and
single-points-of-failure .... including truely
(single-point-of-failure) centralized power. some issue between true
batch and online has to do with availability and real-time
constraints. we coined the term geographic survivability in the late
'80s when starting ha/cmp (to distinquish from disaster/recovery which
had less real-time constraints in various types of batch scenarios).
the are other costs/drivers for high availability ... like service
costs (somewhat driving huge increase in mtbf for COTS hardware drives).
misc. ha/cmp
http://www.garlic.com/~lynn/subtopic.html#hacmp
random others
http://www.garlic.com/~lynn/98.html#35a Drive letters
http://www.garlic.com/~lynn/98.html#37 What is MVS/ESA?
http://www.garlic.com/~lynn/98.html#40 Comparison Cluster vs SMP?
http://www.garlic.com/~lynn/99.html#71 High Availabilty on S/390
http://www.garlic.com/~lynn/99.html#77 Are mainframes relevant ??
http://www.garlic.com/~lynn/99.html#92 MVS vs HASP vs JES (was 2821)
http://www.garlic.com/~lynn/99.html#128 Examples of non-relational databases
http://www.garlic.com/~lynn/2000.html#13 Computer of the century
http://www.garlic.com/~lynn/2000.html#22 Computer of the century
http://www.garlic.com/~lynn/2000c.html#45 Does the word "mainframe" still have a meaning?
http://www.garlic.com/~lynn/2000c.html#47 Does the word "mainframe" still have a meaning?
http://www.garlic.com/~lynn/2000f.html#30 OT?
http://www.garlic.com/~lynn/2000f.html#54 360 Architecture, Multics, ... was (Re: X86 ultimate CISC? No.)
http://www.garlic.com/~lynn/2001b.html#73 7090 vs. 7094 etc.
http://www.garlic.com/~lynn/2001c.html#69 Wheeler and Wheeler
http://www.garlic.com/~lynn/2001d.html#70 Pentium 4 Prefetch engine?
http://www.garlic.com/~lynn/2001d.html#71 Pentium 4 Prefetch engine?
http://www.garlic.com/~lynn/2001e.html#44 Where are IBM z390 SPECint2000 results?
http://www.garlic.com/~lynn/2001g.html#44 The Alpha/IA64 Hybrid
http://www.garlic.com/~lynn/2001i.html#41 Withdrawal Announcement 901-218 - No More 'small machines'
http://www.garlic.com/~lynn/2001i.html#43 Withdrawal Announcement 901-218 - No More 'small machines'
http://www.garlic.com/~lynn/2001i.html#46 Withdrawal Announcement 901-218 - No More 'small machines'
http://www.garlic.com/~lynn/2001i.html#48 Withdrawal Announcement 901-218 - No More 'small machines'
http://www.garlic.com/~lynn/2001i.html#49 Withdrawal Announcement 901-218 - No More 'small machines'
http://www.garlic.com/~lynn/2001j.html#23 OT - Internet Explorer V6.0
http://www.garlic.com/~lynn/2001k.html#13 HP-UX will not be ported to Alpha (no surprise)exit
http://www.garlic.com/~lynn/2001k.html#14 HP-UX will not be ported to Alpha (no surprise)exit
http://www.garlic.com/~lynn/2001k.html#18 HP-UX will not be ported to Alpha (no surprise)exit
http://www.garlic.com/~lynn/2001l.html#47 five-nines
http://www.garlic.com/~lynn/2001n.html#3 News IBM loses supercomputer crown
http://www.garlic.com/~lynn/2001n.html#47 Sysplex Info
http://www.garlic.com/~lynn/2001n.html#85 The demise of compaq
http://www.garlic.com/~lynn/2002h.html#73 Where did text file line ending characters begin?
http://www.garlic.com/~lynn/2002i.html#24 CDC6600 - just how powerful a machine was it?
http://www.garlic.com/~lynn/2002j.html#45 M$ SMP and old time IBM's LCMP
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Large Banking is the only chance for Mainframe
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Large Banking is the only chance for Mainframe
Newsgroups: bit.listserv.ibm-main
Date: Tue, 03 Sep 2002 18:44:23 GMT
IBM-MAIN@ISHAM-RESEARCH.COM (Phil Payne) writes:
I used to regard OS2 as 'MVS on the desktop'. It was pretty well
impossible to get into a situation in which you couldn't collect
debugging information, you could set it to reipl itself if the
'kernel' crashed, and the Workplace Shell was wonderful at
reiniiaising itself and recovering.
I currently have a pernicious memory leak in Outlook Express that
causes two to three boots a day on the Thinkpad.
Linux is starting to mature nicely. I think IBM's presence has
changed a lot of attitudes. We will see.
there used to be a joke about RPS (for s/1) and then OS2 having been
done by os/360 types from the hudson valley that had moved to boca.
They somewhat came into their own on OS2 having a lot more resources
than trying to cram it into the smaller resources of the S/1 (after
start of OS2 timeframe, PCs were starting to outstrip capability of
S/1). It was one of the places where EDX (for s/1) came about. Trying
to cram a 512kbyte, MFT-II/MVT, 24-bit addressing system (RPS) into a
16bit, 64kbyte-128kbyte machine was something more of a challenge.
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
What is microcode?
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: What is microcode?
Newsgroups: comp.arch,alt.folklore.computers
Date: Wed, 04 Sep 2002 06:03:11 GMT
"Foobar T. Clown" writes:
Anyway, during most of that time, a new PC has cost somewhere in the
range of $500 to $2500 with the average, run-of-the-mill product being
just over one grand. What you GET for that price has been pretty much
following Moore's Law, but the PRICE remains the same. I guess it's a
marketing thing.
keyboards, cases, fans, cables, wiring, lots of pieces in the
monitors, cases, trucking costs, labor to demo, answer questions, etc
... haven't been subject to moore's law. i believe it is as much a
packaging cost thing as a marketing thing. i think some have looked at
packaging a motherboard inside a monitor (somewhat like mac) to get
the next cost increment down. the downside is that there is some
varience in consumer demand in monitors ... so consumers are paying
some extra for tailorability.
i vaguely remember some discussion about calculators tending towards a
fixed per key costs (i.e. in volume, calculator price were
proportional to the number of keys).
random refs:
http://www.garlic.com/~lynn/2001n.html#81 a.f.c history checkup... (was What specifications will the standard year 2001 PC have?)
http://www.garlic.com/~lynn/2001n.html#82 a.f.c history checkup... (was What specifications will the standard year 2001 PC have?)
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
ISAs, SMP and hardware optimisations
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: ISAs, SMP and hardware optimisations
Newsgroups: comp.arch
Date: Wed, 04 Sep 2002 15:17:29 GMT
nmm1@cus.cam.ac.uk (Nick Maclaren) writes:
3) A processor is required to make its cache changes visible and
to detect changes in other caches only on the execution of certain
sychronisation instructions (i.e. not loads and stores), and on
certain very heavyweight operations (e.g. a context switch or
non-trivial system call).
there was an attempt to do something like that in the mid-70s with 16
370/158s .... using compare&swap. it works much better in a paradigm
that is heavily message passing and not with paradigm that is heavily
dependent on pointer passing and shared memory. heavy pointer passing
& common/shared memory has certain optimizations but they aggregavate
the cache consistency issue (along with issues of legacy code
migration based on such a paradigm) ... and also has poor fault
isolation characteristics. message passing paradigm has all sorts of
scale up characteristics whether or not memory or real pipes are being
used for transport.
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Computer Architectures
Refed: **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Computer Architectures
Newsgroups: comp.arch,alt.folklore.computers
Date: Thu, 05 Sep 2002 02:14:52 GMT
"glen herrmannsfeldt" writes:
For intel, I would look up the iAPX432.
That is the only one I can think of right now.
post from running across some old 432 books:
http://www.garlic.com/~lynn/2000f.html#48 Famous Machines and Software that didn't
quote in the above from one of the intros ... mentions S/38 ... which
some have considered the refuge of many from the FS project. post
regarding IBM FS ...
http://www.garlic.com/~lynn/2000f.html#16 FS - IBM Future System
the above contains some extracts/quotes from a web page that seems
to be gone.
it also somewhat references that possibly some FS motivations was the
PCMs (plug compatible manufactures). i had help start/launch some of
the original PCM stuff:
http://www.garlic.com/~lynn/subtopic.html#360pcm
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Backdoor in AES ?
Refed: **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Backdoor in AES ?
Newsgroups: sci.crypt
Date: Thu, 05 Sep 2002 14:44:09 GMT
Edward Elliott writes:
Financial systems don't base their security entirely on DES. The
strict auditing trails banks require make your attack unlikely.
i don't know of an actual breach because of DES ... but there is all
sorts of other stuff like skimming:
http://www.garlic.com/~lynn/aepay10.htm#41 ATM Scams -- Whose Liabiilty Is It, Anyway?
somewhat related to going after the easiest method ... direct DES attack
isn't necessarily the easiest method. somewhat similar/related in the case
of SSL and internet stuff
http://www.garlic.com/~lynn/2001h.html#61 Security proportional to risk
http://www.garlic.com/~lynn/2001h.html#58 Net banking, is it safe???
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Free CPU (was: PDP-11 Clones)
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Free CPU (was: PDP-11 Clones)
Newsgroups: comp.arch
Date: Thu, 05 Sep 2002 13:38:57 GMT
Bernd Paysan writes:
The profit margin of a chip is only half of the story. AFAIK, on a fair
calculation basis that includes stock options as "wages" (which they really
are), Intel doesn't make a profit. But so does Microsoft (given how much
their employees make after a few years when selling their stock options,
that's no surprise).
there is a joke in redmond area about some of the early m'soft people
buy up all the real estate in the area very early on. the claim is
that sale of homes on this real estate to m'soft employees exceeds all
salaries paid ... aka m'soft is really just a complex scheme to resell
lots of real estate at significant profit to lots of people.
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Computer Architectures
Refed: **, - **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Computer Architectures
Newsgroups: comp.arch,alt.folklore.computers
Date: Fri, 06 Sep 2002 13:39:22 GMT
"del cecchi" writes:
You really ought to write down the story of FS or get someone else to do
it. I would love to read it.
ref:
http://www.garlic.com/~lynn/2002l.html#19
I was on the outside looking in ... i've posted references before that
i thot it was the case of the inmates in charge of the asylum and the
resulting organization effects caused the pendulum to swing way over
to the opposite side (let's say somewhat all sales). my wife was
relatively fresh out of umich eng grad school and worked for the guy
that "owned" FS I/O at the time (somewhat aside, he had worked on
cp/40 earlier) ... and she thot it was the greatest bluesky sandbox
the world ever invented.
i do remember being told that it was foolish not to want to work on it
.. it would probably hurt my career (also telling them that what I
had running for resource management was better than what they were
designing probably didn't help either).
misc. fs refs:
http://www.garlic.com/~lynn/96.html#24 old manuals
http://www.garlic.com/~lynn/99.html#100 Why won't the AS/400 die? Or, It's 1999 why do I have to learn how to use
http://www.garlic.com/~lynn/2001f.html#30 IBM's "VM for the PC" c.1984??
misc. resource manager:
http://www.garlic.com/~lynn/2002k.html#13 Difference between Unix and Linux?
http://www.garlic.com/~lynn/2002k.html#40 hung/zombie users
http://www.garlic.com/~lynn/2002k.html#46 OT (sort-of) - Does it take math skills to do data processing ?
http://www.garlic.com/~lynn/2002k.html#63 OT (sort-of) - Does it take math skills to do data processing ?
http://www.garlic.com/~lynn/2002k.html#66 OT (sort-of) - Does it take math skills to do data processing ?
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Moore law
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Moore law
Newsgroups: comp.arch
Date: Fri, 06 Sep 2002 13:56:23 GMT
"glen herrmannsfeldt" writes:
Yes. Note that it is the (common) implementation and not the language
that causes this. It is legal in C to do bounds checking even on
dynamically allocated memory, but it is rarely done.
If I ever get to writing a C compiler that generates JVM code
I will be able to test this better. JVM requires bounds
checking on array access.
in some environments ... explicit lengths are implemented on buffers
and strings which can be either handled automagically by run-time
... or the length semantics exposed. in the case of explicitly exposed
length semantics, there is some reduction in vulnerabilities just
because the programmer is reminded to think about length issues.
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Two questions on HMACs and hashing
Refed: **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Two questions on HMACs and hashing
Newsgroups: sci.crypt
Date: Fri, 06 Sep 2002 15:30:28 GMT
Kent Briggs writes:
A digital signature is signed with a private key and authenticated by
anyone with the corresponding public key. A MAC (keyed hash) is signed
and authenticated with a single private key.
let's say digital signature is with a secret, private key ... and a
keyed hash is secret key.
the label digital signature is more referring to a business process
... rather than technology .... the business process of keeping one
part of a asymmetric key-pair really "private" ... in order to
approximate the characteristics of a physical, manual signature (aka
the use of signature in the term "digital signature").
However, there is more to making an approximation to a physical,
manual signature (than just keeping one of the keys
private). typically, a real, physical, manual signature carries with
it the attribute that the person really intended to sign what they
signed.
It is much easier to automate the application of "digital signatures"
where there is no direct human "intention" involved. As a result some
of the uses of asymmetric key technology has depreciated (or
corrupted) the technology from a business sense of "signature".
one of the related characteristics of signature is repudiation. some
repudiation & intention past discussions:
http://www.garlic.com/~lynn/aadsm10.htm#cfppki15 CFP: PKI research workshop
http://www.garlic.com/~lynn/aadsm10.htm#cfppki18 CFP: PKI research workshop
http://www.garlic.com/~lynn/aadsm10.htm#paiin PAIIN security glossary & taxonomy
http://www.garlic.com/~lynn/aadsm11.htm#5 Meaning of Non-repudiation
http://www.garlic.com/~lynn/aadsm11.htm#6 Meaning of Non-repudiation
http://www.garlic.com/~lynn/aadsm11.htm#7 Meaning of Non-repudiation
http://www.garlic.com/~lynn/aadsm11.htm#8 Meaning of Non-repudiation
http://www.garlic.com/~lynn/aadsm11.htm#9 Meaning of Non-repudiation
http://www.garlic.com/~lynn/aadsm11.htm#11 Meaning of Non-repudiation
http://www.garlic.com/~lynn/aadsm11.htm#12 Meaning of Non-repudiation
http://www.garlic.com/~lynn/aadsm11.htm#13 Words, Books, and Key Usage
http://www.garlic.com/~lynn/aadsm11.htm#14 Meaning of Non-repudiation
http://www.garlic.com/~lynn/aadsm11.htm#15 Meaning of Non-repudiation
http://www.garlic.com/~lynn/aadsm11.htm#23 Proxy PKI. Was: IBM alternative to PKI?
http://www.garlic.com/~lynn/aadsm12.htm#0 maximize best case, worst case, or average case? (TCPA)
http://www.garlic.com/~lynn/aadsm12.htm#5 NEWS: 3D-Secure and Passport
http://www.garlic.com/~lynn/aadsm12.htm#12 TOC for world bank e-security paper
http://www.garlic.com/~lynn/aadsm12.htm#19 TCPA not virtualizable during ownership change (Re: Overcoming the potential downside of TCPA)
http://www.garlic.com/~lynn/2001c.html#30 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#34 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#39 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#40 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#41 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#42 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#43 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#44 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#45 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#46 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#47 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#50 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#51 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#52 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#54 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#56 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#57 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#58 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#59 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#60 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#72 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001c.html#73 PKI and Non-repudiation practicalities
http://www.garlic.com/~lynn/2001g.html#11 FREE X.509 Certificates
http://www.garlic.com/~lynn/2001g.html#38 distributed authentication
http://www.garlic.com/~lynn/2001g.html#60 PKI/Digital signature doesn't work
http://www.garlic.com/~lynn/2001g.html#62 PKI/Digital signature doesn't work
http://www.garlic.com/~lynn/2001h.html#51 future of e-commerce
http://www.garlic.com/~lynn/2001j.html#7 No Trusted Viewer possible?
http://www.garlic.com/~lynn/2002f.html#35 Security and e-commerce
http://www.garlic.com/~lynn/2002g.html#37 Security Issues of using Internet Banking
http://www.garlic.com/~lynn/2002g.html#69 Digital signature
http://www.garlic.com/~lynn/2002h.html#13 Biometric authentication for intranet websites?
http://www.garlic.com/~lynn/2002h.html#68 Are you really who you say you are?
http://www.garlic.com/~lynn/2002i.html#67 Does Diffie-Hellman schema belong to Public Key schema family?
http://www.garlic.com/~lynn/2002i.html#77 Does Diffie-Hellman schema belong to Public Key schema family?
http://www.garlic.com/~lynn/2002j.html#24 Definition of Non-Repudiation ?
http://www.garlic.com/~lynn/2002j.html#40 Beginner question on Security
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Do any architectures use instruction count instead of timer
Refed: **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
interrupts for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Fri, 06 Sep 2002 16:52:43 GMT
Christopher Brian Colohan <colohan+@cs.cmu.edu> writes:
A similarly motivated, but not quite as harsh solution is being
explored by the OS research community: I believe both Psycho and K42
have the concept of "hard" and "soft" preemption. The idea is this:
if a user process cooperatively yields the processor, it can do so
more efficiently, since it may know something about it's cache state
or register usage which would allow it to yield at a convenient time.
So when the OS wants a process to yield, instead of taking the CPU
away from the process, it sends it a signal requesting a "soft"
preemption. The process then is allowed to stall for a short time
before actually yielding the CPU. If the process waits too long
before preempting, the OS will "hard" preempt it, which is slightly
less efficient (since it involves a complete state save) but can not
be delayed by the process.
There are all sorts of intersting issues as to how to make a fair
scheduler given this scheme (ie, how do you properly deal with the
process that keeps on saying "just a little bit more time!").
You can find at some information on this if you read the scheduling
white paper on http://researchweb.watson.ibm.com/K42/.
CP/67 and VM/370 always had both i/o interrupt pre-emption and timer
interrupt pre-emption. doing some early work on resource manager on
early 370 cache machines (158s & 168s) noticed big penalty on cache
hits in i/o intensive environments. as a study, the dynamic adaption
stuff was enhanced to turn off i/o interrupts when application
processes were running when the i/o interrupt rate exceed some
threshold.
turns out this was in conjunction with some other kernel
code. nominally most of the cp kernel ran disabled for all interrupts,
but I noticed that a large number of I/O interrupts occured
immediately on dispatching an application process (enabled for
interrupts). So i stuck an "interrupt" (enable/disable) window in the
dispatcher before it went to all the trouble of actually
selecting/marshaling a process for execution.
the dynamic adaptive code then controlled both the "interrupt" window
and whether or not applications/processes were executing with i/o
interrupts enabled.
something similar was seen with some of the early work on 370
"attached processors" ... aka two processor shared memory system
... but only one processor had physical I/O capability. some slight of
hand with early SMP support and how the two processors serialized each
other and handed off work to the appropriate physical processor
... had some interesting results. with hardware monitors tracking
number of instructions executed ... the processor w/o i/o capability
had nearly 50 percent higher MIP rate (and higher cache hit ratio)
than the processor with i/o capability (also lower cache hit ratio).
of course we are talking about a time when caches were in the 8k to
64kbyte range. also the resource manager attempted to adapt the
time-slice to the instruction rate.
random refs:
http://www.garlic.com/~lynn/subtopic.html#smp
http://www.garlic.com/~lynn/subtopic.html#fairshare
http://www.garlic.com/~lynn/subtopic.html#hone
earlier work that i did on cp/67 as undergraudate was playing games
with the amount of work needed to resume the pre-empted task ... much
of the state was saved at interrupt time ... but some could be delayed
until it was decided whether or not a process was going to be resumed.
If it turned out that the pre-empted task was being resumed ... I then
did this stuff I called "fastpath" (i used fastpath for other stuff
... but this is where I started) .... which recognized that much of
the stuff for a resumed pre-empted process didn't have to be
reconstructed from scratch (could vary from 50-90 percent reduction in
kernel overhead).
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Do any architectures use instruction count instead of timer
Refed: **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
interrupts for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Fri, 06 Sep 2002 19:31:07 GMT
gavin@allegro.com (Gavin Scott) writes:
Sounds to me as though you want more control over where the time slices
occur, such as having a system call that says "ok, I'd like not to be
interrupted for the next little while and in exchange I'm willing to
pay a longer time slice in the future", or simply having something like
a yeild() function that says "only give me back the CPU when you can
guarantee I can have the CPU for N microseconds" or something like that.
While you probably can't do much about external interrupts, it would be
interesting to see what having this kind of a yeild() function would let
you do.
note that time-slices have frequently been associated with resource
management. resource management tends to be in terms of wall clock
time ... programs executing more efficient instructions with higher
cache hit ratio shouldn't be penalized compared to programs that have
large proportion of multi-cycle instructions and/or very poor cache
utilization characteristics. invariably if you tried to bias in favor
some factor that might have huge resource use variability (possibly
instructions) ... there would invariably be a pathelogical case either
intentionally or non-intentionally where the operational
characteristics of the system suffered. Some cases, people were
spending as much time progrmaming to vagaries in the resource manager
as they are programming to accomplish the application task.
the opposing trade-off is to avoid pathelogical negative feedback that
because something has lousy instruction/cycle characteristics because
of high cache miss characteristics ... that possibility of "early"
pre-emption further aggravates cache misses.
resource management can encourage better programming practices (better
cache hit ratios, more thruput per unit time, etc) but don't penalize
applications for bad operating system implementation.
one of the things the resource manager offered was standard resource
consumption use (wall-clock) by administrative controls (fair share,
non-share share, etc) ... but could offer less frequent and longer
running (the rate remained about the same ... but the granularity
changed).
random
http://www.garlic.com/~lynn/subtopic.html#fairshare
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
End of Moore's law and how it can influence job market
Refed: **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: End of Moore's law and how it can influence job market .....
Newsgroups: comp.arch
Date: Fri, 06 Sep 2002 19:54:57 GMT
"Rupert Pigott" writes:
Sounds pretty similar to Transputers... AFAIK IBM could even use
the Transputer Trademark if they wished... I don't know enough of
the details of BlueGene to really comment on the specifics though,
I should dig for info. It sounds like my kind of Transputer, 4Kb
never seemed enough, but 4MB seems much more useful. :)
I would kill to work on that project, even as the Janitor. :)
i actually tried to get something going with blue iliad (first 32bit
801) ... that never really got off the ground. i was looking at
surface mount stuff ... but the only place in the US at the time was
TI that was cutting the leads off flush. to get real (both chips and
fabrication machines) surface mount you had to go to the far east. the
other obvious (significant) problem was heat. one issue of surface
mount was populating both sides of the board ... but blue iliad was
so hot that it wasn't practical to put anything on the other side of
the board. i was advocating intermixing ROMAN & ILIAD boards densely
packed in cabinet which also had heat issues (roman was early cmos 370
chip ... about 3mips(?) at the time; not the hacked 68k found in
pc370/washington at 100kips or the 350kips of 7437/a74). The was some
discussion about being able to provide large amount of application
system mips at about 1/10th the current going cost of 370 mips.
ref to some related system work
http://www.garlic.com/~lynn/96.html#4a
a later effort:
http://www.garlic.com/~lynn/95.html#13
random blue iliad:
http://www.garlic.com/~lynn/98.html#25 Merced & compilers (was Re: Effect of speed ... )
http://www.garlic.com/~lynn/99.html#66 System/1 ?
http://www.garlic.com/~lynn/2000.html#16 Computer of the century
http://www.garlic.com/~lynn/2000d.html#60 "all-out" vs less aggressive designs (was: Re: 36 to 32 bit transition)
http://www.garlic.com/~lynn/2002g.html#39 "Soul of a New Machine" Computer?
http://www.garlic.com/~lynn/2002g.html#55 Multics hardware (was Re: "Soul of a New Machine" Computer?)
random pc370/a74 refs:
http://www.garlic.com/~lynn/2000e.html#55 Why not an IBM zSeries workstation?
http://www.garlic.com/~lynn/2000e.html#56 Why not an IBM zSeries workstation?
http://www.garlic.com/~lynn/2001i.html#19 Very CISC Instuctions (Was: why the machine word size ...)
http://www.garlic.com/~lynn/2001i.html#51 DARPA was: Short Watson Biography
http://www.garlic.com/~lynn/2002d.html#4 IBM Mainframe at home
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Two questions on HMACs and hashing
Refed: **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Two questions on HMACs and hashing
Newsgroups: sci.crypt
Date: Fri, 06 Sep 2002 20:12:20 GMT
Michael Sierchio writes:
In the case of a MAC, a third party can't verify a message. That's
the other interesting attribute of digital signatures -- a non-participant
can verify a signature.
or slightly more general; lots of parties can verify a message but
only one party can have generated a specific digital signature
... origin is slightly more deterministic (assuming that business
processes regarding keeping the private key secret have been observed
... note that is still not sufficient for establishing "signature" in
the legal sense; possible to prove where the message/signature
originated ... but not necessarily that there was intention with
regard to the signature).
hmac rather than being secret private key(s) is shared-secret
key(s). infrastructure impacts of single points of compromise can be
mitigated if large scale distribution of shared-secret keys can be
avoided aka systemic failures,
as an aside the typical PKI CADS paradigm associated with asymmetric
keys has its own systemic failure modes ... sales pitch for AADS
paradigm mitigating systemic failure modes:
http://www.garlic.com/~lynn/x959.html#aads
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Do any architectures use instruction count instead of timer
Refed: **, - **, - **, - **, - **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
interrupts for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Sat, 07 Sep 2002 14:35:20 GMT
robertwessel2@yahoo.com (Robert Wessel) writes:
Multiprocessor XA (and later) machines and MVS go out of their way to
do something similar. MVS usually runs only one processor enabled for
I/O interrupts. Further, many I/O "interrupts" (at least on a busy
machine) are handled without actually taking a real interrupt. They
get polled for with the Test-Pending-Interrupt instruction at the tail
of the I/O interrupt handler, and one or two other places.
ref:
http://www.garlic.com/~lynn/2002l.html#25 Do any architectures use instruction count instead of timer
a non-processor related part of studying i/o was getting the resource
manager to dynamically adapt to the "bottleneck" ... over a 10-15 year
period system major bottlenecks shifted from being memory or processor
constrained to be disk constrained. this resulted in my initially
claiming that over a 10 year period that disks showed a significant
decline in relative system thruput ... and then later claiming over a
15 year period the decline in disk relative system performance
declined by an 5-10 times (aka processor and memory increased by
nearly a factor of 50 but disks only increased by possibly a factor of
ten ... so there was a relative decline in disk relative system
thruput). the disk division got really upset by this statement ... and
got the division's system performance group to refute the claim. their
eventual report was that i had actually slightly understated the
decline (it was actually somewhat worse).
that was eventually turned into a presentation given at guide/share
regarding considerations involved in tuning disk i/o infrastructure
(note in extracts in the following, DASD is acronym for "direct access
storage device", aka disks):
http://www.garlic.com/~lynn/2001l.html#40 MVS History (all parts)
past refs:
http://www.garlic.com/~lynn/95.html#8 3330 Disk Drives
http://www.garlic.com/~lynn/95.html#10 Virtual Memory (A return to the past?)
http://www.garlic.com/~lynn/96.html#5 360 "channels" and "multiplexers"?
http://www.garlic.com/~lynn/97.html#18 Why Mainframes?
http://www.garlic.com/~lynn/98.html#6 OS with no distinction between RAM and HD ?
http://www.garlic.com/~lynn/98.html#46 The god old days(???)
http://www.garlic.com/~lynn/99.html#4 IBM S/360
http://www.garlic.com/~lynn/99.html#6 3330 Disk Drives
http://www.garlic.com/~lynn/2000c.html#19 Hard disks, one year ago today
http://www.garlic.com/~lynn/2001c.html#16 database (or b-tree) page sizes
http://www.garlic.com/~lynn/2001c.html#17 database (or b-tree) page sizes
http://www.garlic.com/~lynn/2001f.html#62 any 70's era supercomputers that ran as slow as today's supercomputers?
http://www.garlic.com/~lynn/2001l.html#40 MVS History (all parts)
http://www.garlic.com/~lynn/2001n.html#78 Swap partition no bigger than 128MB?????
http://www.garlic.com/~lynn/2002b.html#1 Microcode? (& index searching)
http://www.garlic.com/~lynn/2002i.html#18 AS/400 and MVS - clarification please
why back in the dark ages when i was an undergraduate ... i had redone
the os/360 mft&mvt sysgens so that the order of system file copying to
new disk(s) ordered them so as to optimize arm seek distances (which
got nearly 3-fold improvement in the majority of the university's
workload).
http://www.garlic.com/~lynn/94.html#18 CP/67 & OS MFT14
http://www.garlic.com/~lynn/94.html#20 CP/67 & OS MFT14
http://www.garlic.com/~lynn/97.html#22 Pre S/360 IBM Operating Systems?
http://www.garlic.com/~lynn/97.html#28 IA64 Self Virtualizable?
http://www.garlic.com/~lynn/98.html#21 Reviving the OS/360 thread (Questions about OS/360)
http://www.garlic.com/~lynn/99.html#93 MVS vs HASP vs JES (was 2821)
http://www.garlic.com/~lynn/99.html#174 S/360 history
http://www.garlic.com/~lynn/2000c.html#10 IBM 1460
http://www.garlic.com/~lynn/2000d.html#50 Navy orders supercomputer
http://www.garlic.com/~lynn/2001.html#26 Disk caching and file systems. Disk history...people forget
http://www.garlic.com/~lynn/2001f.html#26 Price of core memory
http://www.garlic.com/~lynn/2001h.html#12 checking some myths.
http://www.garlic.com/~lynn/2001k.html#37 Is anybody out there still writting BAL 370.
http://www.garlic.com/~lynn/2001l.html#39 is this correct ? OS/360 became MVS and MVS >> OS/390
http://www.garlic.com/~lynn/2002c.html#45 cp/67 addenda (cross-post warning)
I then did a rewrite of the cp/67 arm queuing code from fifo to a
simple elevator type algorithm that would nearly double disk arm
access rate under heavy load.
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Do any architectures use instruction count instead of timer
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
interrupts for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Sat, 07 Sep 2002 14:42:44 GMT
Anne & Lynn Wheeler writes:
that was eventually turned into a presentation given at guide/share
regarding considerations involved in tuning disk i/o infrastructure
(note in extracts in the following, DASD is acronym for "direct access
storage device", aka disks):
http://www.garlic.com/~lynn/2001l.html#40 MVS History (all parts)
oops, finger slip that particular references is:
http://www.garlic.com/~lynn/2001l.html#46 MVS History (all parts)
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Do any architectures use instruction count instead of timer
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
interrupts for context changes?
Newsgroups: alt.folklore.computers
Date: Sat, 07 Sep 2002 15:17:53 GMT
and just a.f.c. posting from year ago ... a 20 year old survey of computers
at CMU, Bell Labs, LBL, Stanford & MIT:
http://www.garlic.com/~lynn/2001l.html#61 MVS History (all parts)
number of 750 & 780s but some number of altos & pergs (& 26 lisp
machines at mit)
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
What is microcode?
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: What is microcode?
Newsgroups: alt.folklore.computers
Date: Sat, 07 Sep 2002 16:37:01 GMT
jmfbahciv writes:
Bunny suits? [emoticon looks at poster with a puzzled
look thinking, "The biz really has gone nuts."]
i had to do a couple hours in bunny suit this summer .... i don't envy
the people that have to do it day-in, day-out, one of the other issues
mentioned was the shoulder fatique from the constant air downflow,
... the pressure isn't significant but effect builds up after awhile.
they've done a lot of work avoiding having to go the next step
... suits that are totally sealed (and their own air supply) .. part
of it is the constant downward air flow.
random ref:
http://www.garlic.com/~lynn/2002j.html#71 history of CMS
a few years ago, my youngest had a summer job on construction crew
building a chip fabrication "clean room" building (in austin, i forget
which one). the outer shell went up and then was "cleaned" ... and
then workers had to observe clean room construction procedures (not
quite bunny suits).
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
misc resource manager related folklore postings
Date: Sat, 07 Sep 2002 10:13:20 -0600
Newsgroups: bit.listserv.vmesa-l
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: misc resource manager related folklore postings
misc. recent resource manager folklore postings (some x-post with ibm-main)
http://www.garlic.com/~lynn/2002k.html#13 Difference between Unix and Linux?
http://www.garlic.com/~lynn/2002k.html#40 hung/zombie users
http://www.garlic.com/~lynn/2002k.html#46 OT (sort-of) - Does it take math skills to do data processing ?
http://www.garlic.com/~lynn/2002k.html#63 OT (sort-of) - Does it take math skills to do data processing ?
http://www.garlic.com/~lynn/2002k.html#66 OT (sort-of) - Does it take math skills to do data processing ?
http://www.garlic.com/~lynn/2002l.html#22 Computer Architectures
http://www.garlic.com/~lynn/2002l.html#25 Do any architectures use instruction count instead of timer
http://www.garlic.com/~lynn/2002l.html#26 Do any architectures use instruction count instead of timer
Do any architectures use instruction count instead of timer
Refed: **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
interrupts for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Sat, 07 Sep 2002 22:47:38 GMT
Anne & Lynn Wheeler writes:
a non-processor related part of studying i/o was getting the resource
manager to dynamically adapt to the "bottleneck" ... over a 10-15 year
period system major bottlenecks shifted from being memory or processor
constrained to be disk constrained. this resulted in my initially
claiming that over a 10 year period that disks showed a significant
decline in relative system thruput ... and then later claiming over a
15 year period the decline in disk relative system performance
declined by an 5-10 times (aka processor and memory increased by
nearly a factor of 50 but disks only increased by possibly a factor of
ten ... so there was a relative decline in disk relative system
thruput). the disk division got really upset by this statement ... and
got the division's system performance group to refute the claim. their
eventual report was that i had actually slightly understated the
decline (it was actually somewhat worse).
the other part of the claim was that in going from cp/67 to vm/hpo
10-15 years later ... if it was a processor issue, the number of
active users should have increased from 80 to 4000 (an increase of
fifty times). since the number of users typically was on the order of
320 (an increase of only four times), there were obviously other
factors in play.
configuration comparision with some ref to CMU, Bell Labs, LBL, Stanford
and MIT
http://www.garlic.com/~lynn/2001l.html#61 MVS History (all parts)
other instances of this discussion:
http://www.garlic.com/~lynn/93.html#31 Big I/O or Kicking the Mainframe out the Door
http://www.garlic.com/~lynn/94.html#43 Bloat, elegance, simplicity and other irrelevant concepts
http://www.garlic.com/~lynn/94.html#55 How Do the Old Mainframes Compare to Today's Micros?
http://www.garlic.com/~lynn/95.html#10 Virtual Memory (A return to the past?)
http://www.garlic.com/~lynn/98.html#46 The god old days(???)
http://www.garlic.com/~lynn/99.html#4 IBM S/360
http://www.garlic.com/~lynn/2001d.html#66 Pentium 4 Prefetch engine?
http://www.garlic.com/~lynn/2001f.html#62 any 70's era supercomputers that ran as slow as today's supercomputers?
http://www.garlic.com/~lynn/2001m.html#23 Smallest Storage Capacity Hard Disk?
http://www.garlic.com/~lynn/2002.html#5 index searching
http://www.garlic.com/~lynn/2002b.html#11 Microcode? (& index searching)
http://www.garlic.com/~lynn/2002b.html#20 index searching
http://www.garlic.com/~lynn/2002e.html#8 What are some impressive page rates?
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Cryptography
Refed: **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Cryptography
Newsgroups: alt.computer.security
Date: Sun, 08 Sep 2002 13:04:41 GMT
"Spelcher" <nope> writes:
I like most everyday people have shrouded a large cloud of mystery around
encryption etc.. then I got to wondering, what if I created a COM object
that took a credit card #, diced it up into for parts, converted to HEX,
times it by a random number, divided it by the amount of seconds until the
year 3000 blah blah blah... kept all necesary puzzle pieces in random places
in a database.. ? Is this is a basic form of cryptography? How could this be
considered unsafe? I can hardly imagine someone going through the trouble of
cracking it, besides the fact that you'd have no access to the hashes
created.
another form of cryptography is to create a standard where every transaction
is digitally signed:
http://www.garlic.com/~lynn/x959.html#x959
then having a business process where the account number can only be
used in an authenticated (signed) transaction eliminates the account
number as a point of attack (i.e. shared-secret).
the current situation is that account number is essentially a shared-secret
but has to be accessed by lots of different business processes by numerous
parties ... meaning that it has to be in the clear:
http://www.garlic.com/~lynn/aadsm6.htm#websecure merchant web server security
http://www.garlic.com/~lynn/aepay7.htm#netbank2 net banking, is it safe?? ... security proportional to risk
http://www.garlic.com/~lynn/aepay7.htm#netsecure some recent threads on netbanking & e-commerce security
http://www.garlic.com/~lynn/aadsm10.htm#cfppki13 CFP: PKI research workshop
http://www.garlic.com/~lynn/aepay10.htm#20 Security Proportional to Risk (was: IBM Mainframe at home)
the problem is that with all the business processes accessing the
number ... that either it has to be stored in the clear in the
database ... or every business process needs the ability to decrypt
the data (as per above ... security proportional to risk threads). If
it is obfuscated/encrypted in the database ... then each of the
business processes becomes a target because each one needs to have the
secret to decrypt the numbers (aka an attack is to copy the whole
database and all the apps) . somewhat related:
http://www.garlic.com/~lynn/2001j.html#5 E-commerce security????
http://www.garlic.com/~lynn/2001j.html#54 Does "Strong Security" Mean Anything?
more general threads:
http://www.garlic.com/~lynn/subtopic.html#fraud
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Do any architectures use instruction count instead of timer
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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
interrupts for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Mon, 09 Sep 2002 14:27:26 GMT
nmm1@cus.cam.ac.uk (Nick Maclaren) writes:
No, no, that is the approach I have been railing against for
years!
What you do is to design a slightly higher-level, more abstract
interface with built-in asynchronicity, zero-copy and explicit
committal semantics. The system-dependent optimisations can then
be done by the driver without reference to the application.
some of the page-mapped stuff have been able to do that ... although
the unix paradigms have been heavy buffer copy. the straight one-level
store implementations started out not having any management semantics
once the mapping operation was performed ... just treated stuff as
simple synchronous page faults. this is one of the places that
TSS360/370 got into trouble. i had done one for cms in the early '70s
that preserved some of the filesystem semantic hints that helped with
asynchronicity & zero copy:
http://www.garlic.com/~lynn/submain.html#mmap
the previous reference to journal file system ... there is journalling
of metadata ... and there are log-structured filesystems. the work by
the bsd fast file system on log-structured filesystem seemed to
indicate that the advantage of writting at the current arm location
was offset by the periodic garbage collection. The is somewhat
independent of the contiguous allocation stuff that as been
traditionally part of the OS/360 (and current descendents) since the
'60s (initial allocation and extents ... potentially multi-cylinder
initial allocation and then extents in either tracks or cylinders).
the one place that log structured types of writes seem to have worked
is with the paging strategy for mvs & vm developed in the early '80s
for big pages. disk space was allocated typically ten times larger
than was going to be used. for writing out ... a full track worth of
4k pages were collected from the same address space (initially for
3380, ten pages) and written as one unit at the current arm position.
Since allocation was sparce (possibly 10 percent) ... there were
always nearby empty tracks to the current arm position. Immediately
trailing the current head position would be full ... as the arm
proceeding sequentially across the disk surface. faults for any page
in a "big page" would bring all pages for the track (and make the
track available). effectively explict garbage collection (as in a
traditional log-structured file system) was eliminated by the
transient nature of pages out on disk.
misc. big page discussions:
http://www.garlic.com/~lynn/2001k.html#60 Defrag in linux? - Newbie question
http://www.garlic.com/~lynn/2002b.html#20 index searching
http://www.garlic.com/~lynn/2002c.html#29 Page size (was: VAX, M68K complex instructions)
http://www.garlic.com/~lynn/2002c.html#48 Swapper was Re: History of Login Names
http://www.garlic.com/~lynn/2002e.html#8 What are some impressive page rates?
http://www.garlic.com/~lynn/2002e.html#11 What are some impressive page rates?
http://www.garlic.com/~lynn/2002f.html#20 Blade architectures
misc log-structured & contiguous refs:
http://www.garlic.com/~lynn/93.html#28 Log Structured filesystems -- think twice
http://www.garlic.com/~lynn/93.html#29 Log Structured filesystems -- think twice
http://www.garlic.com/~lynn/2000.html#93 Predictions and reality: the I/O Bottleneck
http://www.garlic.com/~lynn/2000c.html#24 Hard disks, one year ago today
http://www.garlic.com/~lynn/2000g.html#38 4M pages are a bad idea (was Re: AMD 64bit Hammer CPU and VM)
http://www.garlic.com/~lynn/2001c.html#28 The Foolish Dozen or so in This News Group
http://www.garlic.com/~lynn/2001f.html#59 JFSes: are they really needed?
http://www.garlic.com/~lynn/2001f.html#60 JFSes: are they really needed?
http://www.garlic.com/~lynn/2001m.html#56 Contiguous file system
http://www.garlic.com/~lynn/2001m.html#57 Contiguous file system
http://www.garlic.com/~lynn/2001m.html#58 Contiguous file system
http://www.garlic.com/~lynn/2001n.html#1 More newbie stop the war here!
http://www.garlic.com/~lynn/2001n.html#4 Contiguous file system
http://www.garlic.com/~lynn/2001n.html#62 The demise of compaq
http://www.garlic.com/~lynn/2002.html#5 index searching
http://www.garlic.com/~lynn/2002b.html#20 index searching
http://www.garlic.com/~lynn/2002b.html#37 Poor Man's clustering idea
http://www.garlic.com/~lynn/2001m.html#56 Contiguous file system
http://www.garlic.com/~lynn/2002c.html#29 Page size (was: VAX, M68K complex instructions)
http://www.garlic.com/~lynn/2002d.html#4 IBM Mainframe at home
http://www.garlic.com/~lynn/2002d.html#5 IBM Mainframe at home
http://www.garlic.com/~lynn/2002e.html#32 What goes into a 3090?
http://www.garlic.com/~lynn/2002h.html#52 Bettman Archive in Trouble
http://www.garlic.com/~lynn/2002j.html#66 vm marketing (cross post)
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Computer Architectures
Refed: **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Computer Architectures
Newsgroups: comp.arch,alt.folklore.computers
Date: Mon, 09 Sep 2002 14:42:10 GMT
"Rupert Pigott" writes:
Could have fooled me, I'm still seeing MIPS processors being
produced and new ones popping up ! They lost the benchmarketing
war, but they're still plugging away. :)
as an aside ... the guy that my wife and i reported to when we were
doing HA/CMP had been at motorola before joining the RIOS group and
doing a lot work on first RIOS chipset. When somerset was formed he
headed that up ... and then left to be president of MIPS. in the past
there has been this joke about there only being 200 people in the
industry.
random ha/cmp stuff:
http://www.garlic.com/~lynn/95.html#13
http://www.garlic.com/~lynn/subtopic.html#hacmp
random somerset refs:
http://www.garlic.com/~lynn/2000d.html#60 "all-out" vs less aggressive designs (was: Re: 36 to 32 bit transition)
http://www.garlic.com/~lynn/2001g.html#23 IA64 Rocks My World
http://www.garlic.com/~lynn/2001i.html#28 Proper ISA lifespan?
http://www.garlic.com/~lynn/2001j.html#37 Proper ISA lifespan?
http://www.garlic.com/~lynn/2002g.html#12 "Soul of a New Machine" Computer?
http://www.garlic.com/~lynn/2002g.html#14 "Soul of a New Machine" Computer?
http://www.garlic.com/~lynn/2002i.html#81 McKinley Cometh
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Backdoor in AES ?
Refed: **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Backdoor in AES ?
Newsgroups: sci.crypt
Date: Mon, 09 Sep 2002 15:04:14 GMT
Bryan Olson writes:
As I understand things, triple DES was not approved until the
third revision of FIPS 46. Has NIST or NSA ever approved DESX?
i believe in the past NIST would do FIPS standards from scratch. a
couple years ago ... there was some NIST announcement that NIST would
accept various standards as-is ... without redoing them from
scratch. I believe some of this was done related to X9.62 ecdsa
... for fips186-2. also X9 did a lot of the standards work on
triple-des. misc. pointers to ANSI X9 and ISO TC68:
http://www.garlic.com/~lynn/x959.html#x959
there is also a lot of joint work in biometrics going on in the area
of x9.84 (between X9, NIST, and some other organizations).
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Moore law
Refed: **, - **, - **, - **, - **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Moore law
Newsgroups: comp.arch
Date: Mon, 09 Sep 2002 18:53:13 GMT
Terje Mathisen writes:
a) It is almost always possible to modify the problem in such a way as
to replace a hard problem with something easier.
b) The algorithm is rarely optimal.
c) You can often exchange up-front/batch processing for better
real-time performance. (This is part of what I mean with my .sig)
a couple years ago ... my wife and i got brought in to look at a large
database application (using conventional wisdom implementation) that
if ever deployed was going to take two weeks elapsed time processing
for doing end-of-day work .... and nearly two years elapsed time
processing for doing end-of-month work. we got the end-of-day down to
90 minutes and end-of-month down to under 24hrs (but we had to use a
lot of non-conventional wisdom approaches).
example of going from assembler to interpreted code (and making it
ten times faster with introduction of new optimization):
http://www.garlic.com/~lynn/94.html#11 REXX
http://www.garlic.com/~lynn/2000b.html#32 20th March 2000
http://www.garlic.com/~lynn/2000b.html#33 20th March 2000
http://www.garlic.com/~lynn/2001c.html#0 Z/90, S/390, 370/ESA (slightly off topic)
http://www.garlic.com/~lynn/2002g.html#27 Security Issues of using Internet Banking
http://www.garlic.com/~lynn/2002h.html#37 Computers in Science Fiction
http://www.garlic.com/~lynn/2002k.html#38 GOTOs cross-posting
example of going from assembler to C ... but more than just an
algorithm change .... there was a whole paradigm change in how the
problem was looked at (work redoing "routes" part of large res
system):
http://www.garlic.com/~lynn/96.html#29 Mainframes & Unix
http://www.garlic.com/~lynn/97.html#11 OSes commerical, history
http://www.garlic.com/~lynn/99.html#17 Old Computers
http://www.garlic.com/~lynn/99.html#100 Why won't the AS/400 die? Or, It's 1999 why do I have to learn how to use
http://www.garlic.com/~lynn/99.html#103 IBM 9020 computers used by FAA (was Re: EPO stories (was: HELP IT'S HOT!!!!!))
http://www.garlic.com/~lynn/99.html#136a checks (was S/390 on PowerPC?)
http://www.garlic.com/~lynn/2000f.html#20 Competitors to SABRE?
http://www.garlic.com/~lynn/2001.html#26 Disk caching and file systems. Disk history...people forget
http://www.garlic.com/~lynn/2001.html#62 California DMV
http://www.garlic.com/~lynn/2001d.html#69 Block oriented I/O over IP
http://www.garlic.com/~lynn/2001d.html#74 Pentium 4 Prefetch engine?
http://www.garlic.com/~lynn/2001g.html#45 Did AT&T offer Unix to Digital Equipment in the 70s?
http://www.garlic.com/~lynn/2001g.html#49 Did AT&T offer Unix to Digital Equipment in the 70s?
http://www.garlic.com/~lynn/2001h.html#76 Other oddball IBM System 360's ?
http://www.garlic.com/~lynn/2001j.html#17 I hate Compaq
http://www.garlic.com/~lynn/2001n.html#0 TSS/360
http://www.garlic.com/~lynn/2001n.html#3 News IBM loses supercomputer crown
http://www.garlic.com/~lynn/2002g.html#2 Computers in Science Fiction
http://www.garlic.com/~lynn/2002g.html#3 Why are Mainframe Computers really still in use at all?
http://www.garlic.com/~lynn/2002h.html#12 Why did OSI fail compared with TCP-IP?
http://www.garlic.com/~lynn/2002h.html#43 IBM doing anything for 50th Anniv?
http://www.garlic.com/~lynn/2002i.html#83 HONE
http://www.garlic.com/~lynn/2002j.html#83 Summary: Robots of Doom
various types of just making assembler faster ... including stuff
like "fastpath" (and sometimes a paradigm change):
http://www.garlic.com/~lynn/93.html#1 360/67, was Re: IBM's Project F/S ?
http://www.garlic.com/~lynn/94.html#2 Schedulers
http://www.garlic.com/~lynn/94.html#54 How Do the Old Mainframes
http://www.garlic.com/~lynn/97.html#22 Pre S/360 IBM Operating Systems?
http://www.garlic.com/~lynn/99.html#230 Radius Help help!!!
http://www.garlic.com/~lynn/2001n.html#20 New Virus: Emails sent with no message body and _ prefixed to email address
http://www.garlic.com/~lynn/2002.html#14 index searching
http://www.garlic.com/~lynn/2002c.html#45 cp/67 addenda (cross-post warning)
http://www.garlic.com/~lynn/2002f.html#57 IBM competes with Sun w/new Chips
http://www.garlic.com/~lynn/2002g.html#32 Secure Device Drivers
http://www.garlic.com/~lynn/2002g.html#50 Why did OSI fail compared with TCP-IP?
http://www.garlic.com/~lynn/2002i.html#42 CDC6600 - just how powerful a machine was it?
http://www.garlic.com/~lynn/2002k.html#66 OT (sort-of) - Does it take math skills to do data processing ?
http://www.garlic.com/~lynn/2002l.html#4 why is Kerberos better than this simpler replacement
http://www.garlic.com/~lynn/2002l.html#25 Do any architectures use instruction count instead of timer
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Do any architectures use instruction count instead of timer
Refed: **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **, - **
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Re: Do any architectures use instruction count instead of timer
interrupts for context changes?
Newsgroups: comp.arch,alt.folklore.computers
Date: Mon, 09 Sep 2002 20:16:13 GMT
"Rupert Pigott" writes:
I should have explained, each arm has 8 heads per platter... So
for an 8in diameter drive you'd have a head per 0.5in (max) of platter.
Someone in alt.folklore brought this idea up a few months ago, drives
used to be built like this when arms didn't move. For a 14in the stats
ain't quite as good. But you still get the bandwidth overkill. :)
there were two models of the 2305 fixed head disk .... both had the
same number of heads ... but one had half the heads offset 180 degrees
and only half as many tracks ... and had half the rotational latency.
random 2305 refs:
http://www.garlic.com/~lynn/2001j.html#3 YKYGOW...
http://www.garlic.com/~lynn/2001l.html#53 mainframe question
http://www.garlic.com/~lynn/2001l.html#57 mainframe question
http://www.garlic.com/~lynn/2001l.html#63 MVS History (all parts)
http://www.garlic.com/~lynn/2001m.html#23 Smallest Storage Capacity Hard Disk?
http://www.garlic.com/~lynn/2002.html#22 index searching
http://www.garlic.com/~lynn/2002.html#31 index searching
http://www.garlic.com/~lynn/2002b.html#8 Microcode? (& index searching)
http://www.garlic.com/~lynn/2002b.html#11 Microcode? (& index searching)
then there was the "1655" which was an "electronic memory" simulation of
a 2305 (even lower latency).
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
10 choices that were critical to the Net's success
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: 10 choices that were critical to the Net's success
Newsgroups: alt.folklore.computers
Date: Mon, 09 Sep 2002 21:52:07 GMT
ref:
http://www.siliconvalley.com/mld/siliconvalley/business/columnists/4029770.htm?template=contentModules/printstory.jsp
some comments related to this in different mailing list:
http://www.garlic.com/~lynn/aadsm12.htm#23
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Thirty Years Later: Lessons from the Multics Security Evaluation
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From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: Thirty Years Later: Lessons from the Multics Security Evaluation
Newsgroups: alt.folklore.computers,comp.arch
Date: Mon, 09 Sep 2002 23:08:19 GMT
some of the sections in the paper:
2.2 Security as Standard Product Feature
2.3 No Buffer Overflows
2.4 Minimizing Complexity
http://domino.watson.ibm.com/library/cyberdig.nsf/papers/FDEFBEBC9DD3E35485256C2C004B0F0D/$File/RC22534.pdf
above 404, but now can be found at
http://www.acsac.org/2002/papers/classic-multics.pdf
from the intro in the above:
This Research Report consists of two invited papers for the Classic
Papers section of the 18 th Annual Computer Security Applications
Conference (ACSAC) to be held 9–13 December 2002 in Las Vegas, NV. The
papers will be available on the web after the conference at
http://www.acsac.org/
The first paper, Thirty Years Later: Lessons from the Multics Security
Evaluation, is a commentary on the second paper, discussing the
implications of the second paper's results on contemporary computer
security issues. Copyright will be transferred on the first paper.
The second paper, Multics Security Evaluation: Vulnerability Analysis
is a reprint of a US Air Force report, first published in 1974. It is
a government document, approved for public release, distribution
unlimited, and is not subject to copyright. This reprint does not
include the original computer listings. They can be found at
http://csrc.nist.gov/publications/history/karg74.pdf
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
another 30 year thing
Refed: **, - **, - **, - **
Date: Mon, 09 Sep 2002 18:05:43 -0600
Newsgroups: bit.listserv.vmesa-l
From: Anne & Lynn Wheeler <lynn@garlic.com>
Subject: another 30 year thing
note that this was in the same building (545tech sq) as cp/67 and
initial VM/370 work and shared common heritage back to ctss
http://www.garlic.com/~lynn/2002l.html#42 Thirty Years Later:
other 545 tech. sq related postings:
http://www.garlic.com/~lynn/subtopic.html#545tech
--
Anne & Lynn Wheeler | lynn@garlic.com - http://www.garlic.com/~lynn/
Thirty Years Later: Lessons from the Multics Security Evaluation
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